Architect in the Loop Agentic Hardware Design and Verification
Mubarek Mohammed

TL;DR
This paper introduces an agentic, human-in-the-loop approach to automate hierarchical processor design and verification using generative AI, demonstrated on simple processors with scalable potential for complex systems.
Contribution
It presents a novel agentic framework for automated processor design and verification that integrates engineer guidance, enabling scalable and cost-effective hardware development.
Findings
Successfully designed and verified two simple processors.
Demonstrated cost-effective design using around a million inference tokens.
Showed scalability potential for complex systems like system-on-chip.
Abstract
The ever increasing complexity of the hardware design process demands improved hardware design and verification methodologies. With the advent of generative AI various attempts have been made to automate parts of the design and verification process. Large language models (LLMs) as well as specialized models generate hdl and testbenches for small components, having a few leaf level components. However, there are only a few attempts to automate the entire processor design process. Hardware design demands hierarchical and modular design processes. We utilized this best practice systematically and effectively. We propose agentic automated processor design and verification with engineers in the loop. The agent with optional specification tries to break down the design into sub-components, generate HDL and cocotb tests, and verifies the components involving engineer guidance, especially…
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Taxonomy
TopicsEmbedded Systems Design Techniques · Formal Methods in Verification · Parallel Computing and Optimization Techniques
