VeriPy -- A New Python-Based Approach for SDR Pipelined/Unrolled Hardware Accelerator Generation

TL;DR

VeriPy is a Python-based high-level synthesis tool that simplifies the creation of hardware accelerators for SDR applications, achieving significant performance improvements without requiring hardware expertise.

Contribution

This work introduces VeriPy, a novel Python tool that generates SDR hardware accelerators in Verilog with no need for hardware knowledge or HDL, and includes features like automatic testbench and optimization.

Findings

Achieves up to 70% higher frequency than Vivado HLS with similar resource use.

Requires no pragmas or low-level hardware knowledge.

Maintains comparable code complexity to Vivado HLS for simple algorithms.

Abstract

Software-defined radio (SDR) plays an important role in the communication field by providing a flexible and customized communication system for different purposes according to the needs. To enhance the performance of SDR applications, hardware accelerators have been widely deployed in recent years. In facing this obstacle, a necessity arises for a high-level synthesis (HLS) tool specifically designed for communication engineers without detailed hardware knowledge. To lower the barrier between SDR engineers and hardware development, this work proposed a Python-based HLS tool, VeriPy, which can generate both mainstream architecture for hardware accelerators in Verilog specifically for SDR designs including unrolled design and pipelined design, requiring no detailed digital hardware knowledge or Hardware Description Languages (HDL). Furthermore, VeriPy supports automatic testbench generation with random input stimulus, an extensible hardware library, performance and resource estimation, and offers strong optimisation potential at both the algorithmic and digital hardware levels. The generated hardware design by VeriPy can achieve up to 70% faster operating frequency compared to pragma-optimised Vivado HLS designs with a reasonably higher resource con-sumption while delivering comparable performance and resource consumption to hand-coded implementations. Regarding code complexity, VeriPy requires no pragmas, completely eliminating the need for low-level hardware knowledge. For straightforward algorithms, the input code length remains comparable to that of Vivado HLS.