Sneak Path Current Modeling in Memristor Crossbar Arrays for Analog In-Memory Computing

TL;DR

This paper introduces an analytical model to accurately estimate sneak path currents in memristor crossbar arrays, aiding design optimization for energy-efficient in-memory computing systems.

Contribution

It presents a closed-form analytical framework that captures key parameters affecting sneak path currents, validated with high accuracy and speed, facilitating design and real-time optimization.

Findings

Model achieves less than 10.9% error compared to SPICE simulations.

Model is up to 4784 times faster than full circuit simulations.

Sensitivity analysis reveals trade-offs in array scaling and design parameters.

Abstract

Memristor crossbar arrays have emerged as a key component for next-generation non-volatile memories, artificial neural networks, and analog in-memory computing (IMC) systems. By minimizing data transfer between the processor and memory, they offer substantial energy savings. However, a major design challenge in memristor crossbar arrays is the presence of sneak path currents, which degrade electrical performance, reduce noise margins, and limit reliable operations. This work presents a closed-form analytical framework based on 1.4nm technology for accurately estimating sneak path currents in memristor crossbar arrays. The proposed model captures the interdependence of key design parameters in memristor crossbar arrays, including array size, ON/OFF ratio of memristors, read voltage, and interconnect conditions, through mathematically derived relationships. It supports various practical configurations, such as different data patterns and connection strategies, enabling rapid and comprehensive sneak path current modeling. The sensitivity analysis includes how design parameters influence sneak path current and noise margin loss, underscoring the trade-offs involved in scaling crossbar arrays. Validation through SPICE simulations shows that the model achieves an error of less than 10.9% while being up to 4784 times faster than full circuit simulations. This analytical framework offers a powerful tool for quantitative assessment and pre-design/real-time optimization of memristor-based analog in-memory computing (IMC) architectures.