A 0.32 mm$^2$ 100 Mb/s 223 mW ASIC in 22FDX for Joint Jammer Mitigation, Channel Estimation, and SIMO Data Detection

TL;DR

This paper introduces a compact ASIC that jointly performs jammer mitigation, channel estimation, and data detection for SIMO systems, achieving high throughput and efficiency in jamming scenarios.

Contribution

It presents the first ASIC implementation of the MAED algorithm for joint jammer mitigation, channel estimation, and data detection in a 22nm FD-SOI process.

Findings

Achieves 100 Mb/s throughput at 223 mW power.

Supports eight receive antennas for jammer mitigation.

Outperforms state-of-the-art in throughput and area efficiency.

Abstract

We present the first single-input multiple-output (SIMO) receiver ASIC that jointly performs jammer mitigation, channel estimation, and data detection. The ASIC implements a recent algorithm called siMultaneous mitigAtion, Estimation, and Detection (MAED). MAED mitigates smart jammers via spatial filtering using a nonlinear optimization problem that unifies jammer estimation and nulling, channel estimation, and data detection to achieve state-of-the-art error-rate performance under jamming. The design supports eight receive antennas and enables mitigation of smart jammers as well as of barrage jammers. The ASIC is fabricated in 22 nm FD-SOI, has a core area of 0.32 mm$^2$, and achieves a throughput of 100 Mb/s at 223 mW, thus delivering 3$\times$ higher per-user throughput and 4.5$\times$ higher area efficiency than the state-of-the-art jammer-resilient detector.