A Jammer-Resilient 2.87 mm$^2$ 1.28 MS/s 310 mW Multi-Antenna Synchronization ASIC in 65 nm

TL;DR

This paper introduces a novel ASIC that achieves jammer-resilient multi-antenna synchronization, effectively mitigating smart jammers and supporting high-speed operation in a compact, low-power design.

Contribution

It is the first ASIC implementation of a jammer-resilient multi-antenna synchronization algorithm in 65 nm technology, supporting 16-antenna reception and smart jammer mitigation.

Findings

ASIC size: 2.87 mm²

Power consumption: 310 mW

Sampling rate: 1.28 MS/s

Abstract

We present the first ASIC implementation of jammer-resilient multi-antenna time synchronization. The ASIC implements a recent algorithm that mitigates jamming attacks on synchronization signals using multi-antenna processing. Our design supports synchronization between a single-antenna transmitter and a 16-antenna receiver while mitigating smart jammers with up to two transmit antennas. The fabricated 65 nm ASIC has a core area of 2.87 mm$^2$, consumes a power of 310 mW, and supports a sampling rate of 1.28 mega-samples per second (MS/s).