Bombyx: OpenCilk Compilation for FPGA Hardware Acceleration

TL;DR

Bombyx is a compiler toolchain that translates OpenCilk programs into FPGA-friendly hardware designs, enabling efficient task-level parallelism mapping and high-performance processing element generation for FPGA acceleration.

Contribution

It introduces a novel compilation approach from OpenCilk to FPGA hardware, utilizing explicit continuation-passing and a decoupled access-execute optimization.

Findings

Supports multiple compilation targets including runtime and synthesizable PEs

Improves memory-compute overlap and throughput through access-execute optimization

Enables efficient FPGA mapping of CPU-oriented TLP applications

Abstract

Task-level parallelism (TLP) is a widely used approach in software where independent tasks are dynamically created and scheduled at runtime. Recent systems have explored architectural support for TLP on field-programmable gate arrays (FPGAs), often leveraging high-level synthesis (HLS) to create processing elements (PEs). In this paper, we present Bombyx, a compiler toolchain that lowers OpenCilk programs into a Cilk-1-inspired intermediate representation, enabling efficient mapping of CPU-oriented TLP applications to spatial architectures on FPGAs. Unlike OpenCilk's implicit task model, which requires costly context switching in hardware, Cilk-1 adopts explicit continuation-passing - a model that better aligns with the streaming nature of FPGAs. Bombyx supports multiple compilation targets: one is an OpenCilk-compatible runtime for executing Cilk-1-style code using the OpenCilk backend, and another is a synthesizable PE generator designed for HLS tools like Vitis HLS. Additionally, we introduce a decoupled access-execute optimization that enables automatic generation of high-performance PEs, improving memory-compute overlap and overall throughput.