QiMeng-CRUX: Narrowing the Gap Between Natural Language and Verilog via Core Refined Understanding eXpression for Circuit Design

TL;DR

This paper introduces CRUX, a structured intermediate representation for hardware description language generation that improves the accuracy and transferability of Verilog code from natural language descriptions.

Contribution

We propose CRUX, a novel structured intermediate space, and a two-stage training framework to enhance natural language to Verilog code generation.

Findings

CRUX-V achieves state-of-the-art results on Verilog benchmarks.

CRUX space improves transferability and prompt effectiveness for code models.

Our approach effectively narrows the gap between natural language and Verilog code generation.

Abstract

Large language models (LLMs) have shown promising capabilities in hardware description language (HDL) generation. However, existing approaches often rely on free-form natural language descriptions that are often ambiguous, redundant, and unstructured, which poses significant challenges for downstream Verilog code generation. We treat hardware code generation as a complex transformation from an open-ended natural language space to a domain-specific, highly constrained target space. To bridge this gap, we introduce Core Refined Understanding eXpression (CRUX), a structured intermediate space that captures the essential semantics of user intent while organizing the expression for precise Verilog code generation. We further design a two-stage training framework, comprising Joint Expression Modeling and Dual-Space Optimization, to enhance the quality of both CRUX and Verilog code. Experiments across multiple Verilog generation benchmarks demonstrate that our model, CRUX-V, achieves state-of-the-art performance among general models, particularly under challenging design tasks. Furthermore, the CRUX space proves transferable and beneficial when used as input prompts for other code models, highlighting its effectiveness in narrowing the gap between free-form natural language descriptions and precise Verilog generation.