SARA: A Stall-Aware Memory Allocation Strategy for Mixed-Criticality Systems
Meng-Chia Lee, Wen Sheng Lim, Yuan-Hao Chang, Tei-Wei Kuo

TL;DR
SARA is a stall-aware memory allocator designed for mixed-criticality edge systems, optimizing memory distribution to meet real-time deadlines and improve overall throughput under constrained memory conditions.
Contribution
It introduces a novel stall-aware memory allocation strategy that balances real-time and non-real-time tasks, reducing stalls and enhancing system performance in memory-limited environments.
Findings
Achieves 97.13% deadline hit ratio for soft RT tasks.
Improves non-RT throughput by up to 22.32x.
Operates effectively with only 60% of peak memory demand.
Abstract
The memory capacity in edge devices is often limited due to constraints on cost, size, and power. Consequently, memory competition leads to inevitable page swapping in memory-constrained mixed-criticality edge devices, causing slow storage I/O and thus performance degradation. In such scenarios, inefficient memory allocation disrupts the balance between application performance, causing soft real-time (soft RT) tasks to miss deadlines or preventing non-real-time (non-RT) applications from optimizing throughput. Meanwhile, we observe unpredictable, long system-level stalls (called long stalls) under high memory and I/O pressure, which further degrade performance. In this work, we propose a Stall-Aware Real-Time Memory Allocator (SARA), which discovers opportunities for performance balance by allocating just enough memory to soft RT tasks to meet deadlines and, at the same time, optimizing…
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Taxonomy
TopicsParallel Computing and Optimization Techniques · Real-Time Systems Scheduling · Advanced Data Storage Technologies
