Parameterized Verification of Quantum Circuits (Technical Report)
Parosh Aziz Abdulla, Yu-Fang Chen, Michal He\v{c}ko, Luk\'a\v{s} Hol\'ik, Ond\v{r}ej Leng\'al, Jyun-Ao Lin, Ramanathan S. Thinniyam

TL;DR
This paper introduces an automatic framework for verifying relational properties of parameterized quantum programs using a novel automata model, enabling efficient verification of quantum circuit correctness and equivalence.
Contribution
It presents a new automata-based approach with SWTAs and transducers for verifying parameterized quantum programs, a first in the field.
Findings
Successfully verified diverse quantum programs within seconds
Demonstrated the expressiveness of the automata model
Provided decision procedures for equivalence checking
Abstract
We present the first fully automatic framework for verifying relational properties of parameterized quantum programs, i.e., a program that, given an input size, generates a corresponding quantum circuit. We focus on verifying input-output correctness as well as equivalence. At the core of our approach is a new automata model, synchronized weighted tree automata (SWTAs), which compactly and precisely captures the infinite families of quantum states produced by parameterized programs. We introduce a class of transducers to model quantum gate semantics and develop composition algorithms for constructing transducers of parameterized circuits. Verification is reduced to functional inclusion or equivalence checking between SWTAs, for which we provide decision procedures. Our implementation demonstrates both the expressiveness and practical efficiency of the framework by verifying a diverse…
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Taxonomy
TopicsQuantum Computing Algorithms and Architecture · Formal Methods in Verification · Complexity and Algorithms in Graphs
