GROOT: Graph Edge Re-growth and Partitioning for the Verification of Large Designs in Logic Synthesis
Kiran Thorat, Hongwu Peng, Yuebo Luo, Xi Xie, Shaoyi Huang, Amit Hasan, Jiahui Zhao, Yingjie Li, Zhijie Shi, Cunxi Yu, Caiwen Ding
TL;DR
GROOT is a novel framework combining chip design knowledge, graph theory, and GPU optimization to efficiently verify large-scale circuits with high accuracy and reduced memory usage.
Contribution
It introduces a joint system and algorithm design for graph partitioning, edge re-growth, and GPU kernel optimization tailored for large circuit verification.
Findings
Achieves 59.38% reduction in memory footprint.
Attains 99.96% verification accuracy on large circuits.
Improves runtime by up to 5.796x over state-of-the-art methods.
Abstract
Traditional verification methods in chip design are highly time-consuming and computationally demanding, especially for large scale circuits. Graph neural networks (GNNs) have gained popularity as a potential solution to improve verification efficiency. However, there lacks a joint framework that considers all chip design domain knowledge, graph theory, and GPU kernel designs. To address this challenge, we introduce GROOT, an algorithm and system co-design framework that contains chip design domain knowledge and redesigned GPU kernels, to improve verification efficiency. More specifically, we create node features utilizing the circuit node types and the polarity of the connections between the input edges to nodes in And-Inverter Graphs (AIGs). We utilize a graph partitioning algorithm to divide the large graphs into smaller sub-graphs for fast GPU processing and develop a graph edge…
Peer Reviews
Decision·ICLR 2025 Conference Withdrawn Submission
The paper tries to address a relevant problem and is well written, and well organized.
1) The reliance on partitioning and boundary edge re-growth introduces a trade-off between memory efficiency and accuracy. Specifically, as the number of partitions increases, accuracy tends to drop, particularly for complex graphs like Booth multipliers. This suggests that the edge re-growth algorithm may struggle to fully restore the lost connectivity and feature flow between partitions, which could lead to verification errors or degraded GNN performance in highly partitioned graphs. 2) GROOT’
-This work presents a degree-based graph partitioning algorithm to split high-degree nodes and low-degree nodes for more efficient GPU optimization respectively. -This work presents very impressive performance speedup over baseline implementions.
-This authors argue that the proposed framework has domain specific knowledge included into the GNN optimization. However, the proposed circuit specific optimization including degree-based graph partitioning and node type classification are not new and they are already well studied in prior graph processing and GNN modeling. In addition, these optimizations are mostly specific to the graph structures and it is not quite relevant to the underlying EDA tasks. Although these approaches do enhance
+ Logic synthesis is critical for chip design by converting high-level circuit descriptions into optimized gate-level implementations + A benchmark is created and numerous experimental simulations were run to showcase the scalability of the GROOT
- Little information if any is provided behind the reasons of the proposed approach and how it is inspired or improves algorithmically over existing approaches. - Ablation studies, analysis of the results and implications are incomplete or need a comprehensive restructuring.
1. The proposed method successfully handles very large circuits with 134 million nodes and 268 million edges, achieving a high accuracy of 99.96%. 2. The novel GPU kernel designs leverage node degree properties, with the HD-Kernel for high-degree nodes and the LD-Kernel for low-degree nodes, delivering state-of-the-art runtime performance.
1. The related work section could be expanded for a more comprehensive comparison. The paper focuses primarily on comparing with GAMORA as the state-of-the-art, but there are numerous other GNNs in the EDA domain, such as HOGA [1] and DeepGate2 [2]. Additionally, the comparison only considers memory and runtime metrics with GAMORA, whereas it would be beneficial to also compare accuracy with other methods. 2. The paper lacks an ablation study, which is crucial for understanding the contribution
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Taxonomy
TopicsEmbedded Systems Design Techniques · Low-power high-performance VLSI design · VLSI and FPGA Design Techniques