Optimized Memory Tagging on AmpereOne Processors
Shivnandan Kaushik, Mahesh Madhav, Nagi Aboulenein, Jason Bessette, Sandeep Brahmadathan, Benjamin Chaffin, Matthew Erler, Stephan Jourdan, Thomas Maciukenas, Ramya Jayaram Masti, Jon Perry, Massimo Sutera, Scott Tetrick, Bret Toll, David Turley, Carl Worth, Atiq Bajwa

TL;DR
This paper presents an optimized implementation of Memory Tagging Extension (MTE) on AmpereOne datacenter processors, achieving low overhead and high security for memory safety in cloud workloads.
Contribution
It introduces a hardware-efficient MTE implementation on AmpereOne that incurs no memory overhead and offers minimal performance impact, along with analysis of software optimization opportunities.
Findings
No memory capacity overhead for tag storage.
Single-digit performance impact across workloads.
Hardware-software stack analysis reveals software as a key overhead source.
Abstract
Memory-safety escapes continue to form the launching pad for a wide range of security attacks, especially for the substantial base of deployed software that is coded in pointer-based languages such as C/C++. Although compiler and Instruction Set Architecture (ISA) extensions have been introduced to address elements of this issue, the overhead and/or comprehensive applicability have limited broad production deployment. The Memory Tagging Extension (MTE) to the ARM AArch64 Instruction Set Architecture is a valuable tool to address memory-safety escapes; when used in synchronous tag-checking mode, MTE provides deterministic detection and prevention of sequential buffer overflow attacks, and probabilistic detection and prevention of exploits resulting from temporal use-after-free pointer programming bugs. The AmpereOne processor, launched in 2024, is the first datacenter processor to…
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