ATMPlace: Analytical Thermo-Mechanical-Aware Placement Framework for 2.5D-IC

TL;DR

ATMPlace is an analytical placement framework for 2.5D integrated circuits that optimizes wirelength, thermal, and mechanical reliability efficiently, enabling scalable design exploration for complex chiplet systems.

Contribution

It introduces the first physics-based analytical placer for 2.5D ICs that jointly optimizes multiple critical factors, surpassing traditional methods in speed and quality.

Findings

146% wirelength improvement over TAP 2.5D

3-13% lower peak temperature

5-27% less warpage

Abstract

Rising demand in AI and automotive applications is accelerating 2.5D IC adoption, with multiple chiplets tightly placed to enable high-speed interconnects and heterogeneous integration. As chiplet counts grow, traditional placement tools, limited by poor scalability and reliance on slow simulations, must evolve beyond wirelength minimization to address thermal and mechanical reliability, critical challenges in heterogeneous integration. In this paper, we present ATMPlace, the first analytical placer for 2.5D ICs that jointly optimizes wirelength, peak temperature, and operational warpage using physics-based compact models. It generates Pareto optimal placements for systems with dozens of chiplets. Experimental results demonstrate superior performance: 146 percent and 52 percent geometric mean wirelength improvement over TAP 2.5D and TACPlace, respectively, with 3 to 13 percent lower temperature and 5 to 27 percent less warpage, all achieved approximately 10 times faster. The proposed framework is general and can be extended to enable fast, scalable, and reliable design exploration for next-generation 2.5D systems.