Medusa: Detecting and Removing Failures for Scalable Quantum Computing

TL;DR

Medusa is an automated compilation technique that reduces quantum circuit failure rates by using flags to predict and lower high-weight errors, improving fault-tolerance and lowering error correction costs in scalable quantum computing.

Contribution

We introduce Medusa, a novel method that uses flags to predict and bound failure rates, enabling more fault-tolerant and scalable quantum circuits.

Findings

Medusa effectively lowers failure rates in quantum circuits.

Flag-based fault-tolerance improves circuit reliability.

Numerical results show reduced error correction costs.

Abstract

Quantum circuits will experience failures that lead to computational errors. We introduce Medusa, an automated compilation method for lowering a circuit's failure rate. Medusa uses flags to predict the absence of high-weight errors. Our method can numerically upper bound the failure rate of a circuit in the presence of flags, and fine tune the fault-tolerance of the flags in order to reach this bound. We assume the flags can have an increased fault-tolerance as a result of applying surface QECs to the gates interacting with them. We use circuit level depolarizing noise to evaluate the effectiveness of these flags in revealing the absence of the high-weight stabilizers. Medusa reduces the cost of quantum-error-correction (QEC) because the underlying circuit has a lower failure rate. We benchmark our approach using structured quantum circuits representative of ripple-carry adders. In particular, our flag scheme demonstrates that for adder-like circuits, the failure rate of large-scale implementations can be lowered to fit the failure rates of smaller-scale circuits. We show numerically that a slight improvement in the local fault-tolerance of the flag-qubits can lead to a reduction in the overall failure rate of the entire quantum circuit.