TRAM: A Transverse Relaxation Time-Aware Qubit Mapping Algorithm for NISQ Devices

TL;DR

TRAM introduces a coherence-aware qubit mapping algorithm for NISQ devices that considers T2 relaxation times, significantly improving quantum circuit fidelity and efficiency by dynamically optimizing qubit placement and routing.

Contribution

It is the first to incorporate transverse relaxation times into qubit mapping, enhancing noise resilience in quantum circuit compilation for NISQ devices.

Findings

TRAM outperforms SABRE with 3.59% higher fidelity.

Reduces gate count by 11.49%.

Shortens circuit depth by 12.28%.

Abstract

Noisy intermediate-scale quantum (NISQ) devices impose dual challenges on quantum circuit execution: limited qubit connectivity requires extensive SWAP-gate routing, while time-dependent decoherence progressively degrades quantum information. Existing qubit mapping algorithms optimize for hardware topology and static calibration metrics but systematically neglect transverse relaxation dynamics (T2), creating a fundamental gap between compiler decisions and evolving noise characteristics. We present TRAM (Transverse Relaxation Time-Aware Qubit Mapping), a coherence-guided compilation framework that elevates decoherence mitigation to a primary optimization objective. TRAM integrates calibration-informed community detection to construct noise-resilient qubit partitions, generates time-weighted initial mappings that anticipate coherence decay, and dynamically schedules SWAP operations to minimize cumulative error accumulation. Evaluated on Qiskit-based simulators with realistic noise models, TRAM outperforms SABRE by 3.59% in fidelity, reduces gate count by 11.49%, and shortens circuit depth by 12.28%, establishing coherence-aware optimization as essential for practical quantum compilation in the NISQ era.