Toward Open-Source Chiplets for HPC and AI: Occamy and Beyond

TL;DR

This paper outlines a roadmap for developing open-source chiplet-based RISC-V systems for HPC and AI, highlighting recent advancements from Occamy to Ogopogo and discussing future openness extensions.

Contribution

It introduces a series of open-source chiplet designs for RISC-V systems, demonstrating scalable architectures from 12nm to 7nm technology nodes.

Findings

First open, silicon-proven dual-chiplet RISC-V manycore in 12nm

Development of a mesh-NoC dual-chiplet system (Ramora)

Design of a 7nm quad-chiplet architecture (Ogopogo) with high compute density

Abstract

We present a roadmap for open-source chiplet-based RISC-V systems targeting high-performance computing and artificial intelligence, aiming to close the performance gap to proprietary designs. Starting with Occamy, the first open, silicon-proven dual-chiplet RISC-V manycore in 12nm FinFET, we scale to Ramora, a mesh-NoC-based dual-chiplet system, and to Ogopogo, a 7nm quad-chiplet concept architecture achieving state-of-the-art compute density. Finally, we explore possible avenues to extend openness beyond logic-core RTL into simulation, EDA, PDKs, and off-die PHYs.