A Novel Pixel-Chip-Based Region-of-Interest Readout Circuit Design

TL;DR

This paper introduces the ROIRC, a new pixel chip readout scheme for large arrays that quickly detects and prioritizes signal regions, reducing unnecessary data readout and enabling efficient low-energy X-ray detection.

Contribution

The paper presents the design and implementation of ROIRC, a novel readout circuit that improves speed and efficiency for large-area pixel chips and Gas Pixel Detectors.

Findings

Successfully implemented on ASIC and FPGA platforms

Capable of detecting low-energy X-rays (2-10 keV)

Supports high event count rates up to 15k / (cm2 x s)

Abstract

This paper presents a novel pixel chip readout scheme: the Region-of-Interest Readout Circuit (ROIRC), which is designed for large area, large array pixel chips and Gas Pixel Detector (GPD). This design employs a sentinel pixel detection strategy, enabling rapid identification and prioritized readout of the pixel regions containing signal events. During the scanning readout of these signal events, ROIRC employs a Block-based readout approach, effectively minimizing the readout of non-signal pixels. The functionality of ROIRC has been successfully implemented on both the ASIC and FPGA platforms. In the tests of the ROIRC, the pixel chip embedded in the GPD is capable of detecting low-energy X-rays in the range of 2-10 keV and supports multiple event readouts, and the pixel chip can read out photo-electron signal events with the count rate up to 15k / (cm2 x s).