Cement2: Temporal Hardware Transactions for High-Level and Efficient FPGA Programming
Youwei Xiao, Zizhang Luo, Weijie Peng, Yuyang Zou, Yun Liang

TL;DR
Cement2 introduces a novel transactional HDL with cycle-level timing awareness, enabling high-level, efficient FPGA programming of complex hardware components without performance loss.
Contribution
It presents temporal hardware transactions in Cement2, a Rust-embedded HDL, allowing multi-cycle behavior modeling and improving FPGA design productivity.
Findings
Achieves comparable performance to hand-coded RTL.
Supports complex hardware components like RISC-V cores and accelerators.
Enhances FPGA programming productivity with high-level abstractions.
Abstract
Hardware design faces a fundamental challenge: raising abstraction to improve productivity while maintaining control over low-level details like cycle accuracy. Traditional RTL design in languages like SystemVerilog composes modules through wiring-style connections that provide weak guarantees for behavioral correctness. While high-level synthesis (HLS) and emerging abstractions attempt to address this, they either introduce unpredictable overhead or restrict design generality. Although transactional HDLs provide a promising foundation by lifting design abstraction to atomic and composable rules, they solely model intra-cycle behavior and do not reflect the native temporal design characteristics, hindering applicability and productivity for FPGA programming scenarios. We propose temporal hardware transactions, a new abstraction that brings cycle-level timing awareness to designers at…
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Taxonomy
TopicsEmbedded Systems Design Techniques · Parallel Computing and Optimization Techniques · Formal Methods in Verification
