SynapticCore-X: A Modular Neural Processing Architecture for Low-Cost FPGA Acceleration

TL;DR

SynapticCore-X introduces a modular, resource-efficient neural processing architecture optimized for low-cost FPGAs, enabling flexible, open-source neural acceleration with validated performance and low resource consumption.

Contribution

It presents a fully open-source, configurable FPGA-based neural processing architecture with a streamlined microarchitecture and automated build pipeline, facilitating rapid hardware-software co-design exploration.

Findings

Achieves timing closure at 100 MHz on Zynq-7020

Consumes only 6.1% LUTs, 32.5% DSPs, 21.4% BRAMs

Validated on PYNQ-Z2 with cycle-accurate performance

Abstract

This paper presents SynapticCore-X, a modular and resource-efficient neural processing architecture optimized for deployment on low-cost FPGA platforms. The design integrates a lightweight RV32IMC RISC-V control core with a configurable neural compute tile that supports fused matrix, activation, and data-movement operations. Unlike existing FPGA accelerators that rely on heavyweight IP blocks, SynapticCore-X provides a fully open-source SystemVerilog microarchitecture with tunable parallelism, scratchpad memory depth, and DMA burst behavior, enabling rapid exploration of hardware-software co-design trade-offs. We document an automated, reproducible Vivado build pipeline that achieves timing closure at 100 MHz on the Zynq-7020 while consuming only 6.1% LUTs, 32.5% DSPs, and 21.4% BRAMs. Hardware validation on PYNQ-Z2 confirms correct register-level execution, deterministic control-path behavior, and cycle-accurate performance for matrix and convolution kernels. SynapticCore-X demonstrates that energy-efficient NPU-like acceleration can be prototyped on commodity educational FPGAs, lowering the entry barrier for academic and open-hardware research in neural microarchitectures.