HeteroSTA: A CPU-GPU Heterogeneous Static Timing Analysis Engine with Holistic Industrial Design Support

TL;DR

HeteroSTA is a novel CPU-GPU heterogeneous timing analysis engine that offers versatile accuracy-speed models, industry format support, and end-to-end GPU acceleration, significantly improving runtime performance for industrial applications.

Contribution

It introduces the first CPU-GPU heterogeneous timing analysis engine with flexible models, comprehensive industry format support, and integrated GPU acceleration, enabling faster and more versatile timing analysis.

Findings

Significant runtime speed-up demonstrated in practical applications.

Supports industry-standard formats including .sdc constraints.

Provides comparable quality to existing tools with enhanced efficiency.

Abstract

We introduce in this paper, HeteroSTA, the first CPU-GPU heterogeneous timing analysis engine that efficiently supports: (1) a set of delay calculation models providing versatile accuracy-speed choices without relying on an external golden tool, (2) robust support for industry formats, including especially the .sdc constraints containing all common timing exceptions, clock domains, and case analysis modes, and (3) end-to-end GPU-acceleration for both graph-based and path-based timing queries, all exposed as a zero-overhead flattened heterogeneous application programming interface (API). HeteroSTA is publicly available with both a standalone binary executable and an embeddable shared library targeting ubiquitous academic and industry applications. Example use cases as a standalone tool, a timing-driven DREAMPlace 4.0 integration, and a timing-driven global routing integration have all demonstrated remarkable runtime speed-up and comparable quality.