Tiny Chiplets Enabled by Packaging Scaling: Opportunities in ESD Protection and Signal Integrity

TL;DR

This paper explores how advanced packaging scaling enables the creation of tiny chiplets by simplifying ESD protection and signaling, leading to smaller, more reusable chiplets for high-density 2.5D/3D systems.

Contribution

It demonstrates that ESD and signaling circuitry can be significantly simplified in future packaging technologies, facilitating chiplet miniaturization.

Findings

ESD protection and signaling can be simplified in future packaging.

Simplification enables further chiplet miniaturization.

Improves chiplet reusability and system integration.

Abstract

The scaling of advanced packaging technologies provides abundant interconnection resources for 2.5D/3D heterogeneous integration (HI), thereby enabling the construction of larger-scale VLSI systems with higher energy efficiency in data movement. However, conventional input/output (I/O) circuitry, including electrostatic discharge (ESD) protection and signaling, introduces significant area overhead. Prior studies have identified this overhead as a major constraint in reducing chiplet size below 100 mm2. In this study, we revisit reliability requirements from the perspective of chiplet interface design. Through parasitic extraction and simulation program with integrated circuit emphasis (SPICE) simulations, we demonstrate that ESD protection and inter-chiplet signaling can be substantially simplified in future 2.5D/3D packaging technologies. Such simplification, in turn, paves the road for further chiplet miniaturization and improves the composability and reusability of tiny chiplets.