Beamspace Equalization for mmWave Massive MIMO: Algorithms and VLSI Implementations

TL;DR

This paper introduces beamspace equalization algorithms and VLSI architectures for mmWave massive MIMO, significantly reducing power consumption and increasing throughput by leveraging channel sparsity.

Contribution

It proposes new beamspace data detection algorithms and VLSI designs that outperform existing solutions in power efficiency and throughput for mmWave massive MIMO systems.

Findings

Up to 54% power savings with the proposed CSPADE equalizer.

Achieves highest throughput among existing massive MIMO detectors.

Up to 66% power savings with MAC-based CSPADE architecture.

Abstract

Massive multiuser multiple-input multiple-output (MIMO) and millimeter-wave (mmWave) communication are key physical layer technologies in future wireless systems. Their deployment, however, is expected to incur excessive baseband processing hardware cost and power consumption. Beamspace processing leverages the channel sparsity at mmWave frequencies to reduce baseband processing complexity. In this paper, we review existing beamspace data detection algorithms and propose new algorithms as well as corresponding VLSI architectures that reduce data detection power. We present VLSI implementation results for the proposed architectures in a 22nm FDSOI process. Our results demonstrate that a fully-parallelized implementation of the proposed complex sparsity-adaptive equalizer (CSPADE) achieves up to 54% power savings compared to antenna-domain equalization. Furthermore, our fully-parallelized designs achieve the highest reported throughput among existing massive MIMO data detectors, while achieving better energy and area efficiency. We also present a sequential multiply-accumulate (MAC)-based architecture for CSPADE, which enables even higher power savings, i.e., up to 66%, compared to a MAC-based antenna-domain equalizer.