DynamicRTL: RTL Representation Learning for Dynamic Circuit Behavior

TL;DR

This paper introduces DR-GNN, a novel graph neural network model that captures dynamic circuit behavior at the RTL level, improving tasks like verification, power estimation, and assertion prediction by incorporating multi-cycle execution data.

Contribution

The paper presents DR-GNN, the first GNN model to integrate static RTL structures with dynamic execution behaviors, along with a comprehensive dataset of over 6,300 designs and 63,000 traces.

Findings

DR-GNN outperforms existing models in branch hit prediction.

It achieves higher accuracy in toggle rate prediction.

Learned representations transfer effectively to power estimation and assertion prediction tasks.

Abstract

There is a growing body of work on using Graph Neural Networks (GNNs) to learn representations of circuits, focusing primarily on their static characteristics. However, these models fail to capture circuit runtime behavior, which is crucial for tasks like circuit verification and optimization. To address this limitation, we introduce DR-GNN (DynamicRTL-GNN), a novel approach that learns RTL circuit representations by incorporating both static structures and multi-cycle execution behaviors. DR-GNN leverages an operator-level Control Data Flow Graph (CDFG) to represent Register Transfer Level (RTL) circuits, enabling the model to capture dynamic dependencies and runtime execution. To train and evaluate DR-GNN, we build the first comprehensive dynamic circuit dataset, comprising over 6,300 Verilog designs and 63,000 simulation traces. Our results demonstrate that DR-GNN outperforms existing models in branch hit prediction and toggle rate prediction. Furthermore, its learned representations transfer effectively to related dynamic circuit tasks, achieving strong performance in power estimation and assertion prediction.