Event-Driven Digital-Time-Domain Inference Architectures for Tsetlin Machines

TL;DR

This paper introduces a novel digital-time-domain architecture for Tsetlin Machines that significantly reduces energy consumption and increases throughput by replacing complex arithmetic with delay-based mechanisms.

Contribution

It presents a new delay accumulation and Winner-Takes-All scheme for TMs, enabling efficient inference without extensive arithmetic computations.

Findings

Orders-of-magnitude energy efficiency improvements

Significant throughput enhancement

Effective handling of binary-signed and exponential delays

Abstract

Machine learning fits model parameters to approximate input-output mappings, predicting unknown samples. However, these models often require extensive arithmetic computations during inference, increasing latency and power consumption. This paper proposes a digital-time-domain computing approach for Tsetlin machine (TM) inference process to address these challenges. This approach leverages a delay accumulation mechanism to mitigate the costly arithmetic sums of classes and employs a Winner-Takes-All scheme to replace conventional magnitude comparators. Specifically, a Hamming distance-driven time-domain scheme is implemented for multi-class TMs. Furthermore, differential delay paths, combined with a leading-ones-detector logarithmic delay compression digital-time-domain scheme, are utilised for the coalesced TMs, accommodating both binary-signed and exponential-scale delay accumulation issues. Compared to the functionally equivalent, post-implementation digital TM architecture baseline, the proposed architecture demonstrates orders-of-magnitude improvements in energy efficiency and throughput.