GRACE: Designing Generative Face Video Codec via Agile Hardware-Centric Workflow

TL;DR

This paper introduces an FPGA-based deployment scheme for generative face video codecs, significantly improving energy efficiency and adaptability for edge devices through hardware-software co-design and network compression techniques.

Contribution

It presents the first FPGA-oriented deployment framework for AGC, combining network compression and specialized hardware design to optimize energy efficiency and performance on edge platforms.

Findings

Achieved 24.9× higher energy efficiency than CPU

Achieved 4.1× higher energy efficiency than GPU

Only 11.7 microjoules per pixel reconstructed

Abstract

The Animation-based Generative Codec (AGC) is an emerging paradigm for talking-face video compression. However, deploying its intricate decoder on resource and power-constrained edge devices presents challenges due to numerous parameters, the inflexibility to adapt to dynamically evolving algorithms, and the high power consumption induced by extensive computations and data transmission. This paper for the first time proposes a novel field programmable gate arrays (FPGAs)-oriented AGC deployment scheme for edge-computing video services. Initially, we analyze the AGC algorithm and employ network compression methods including post-training static quantization and layer fusion techniques. Subsequently, we design an overlapped accelerator utilizing the co-processor paradigm to perform computations through software-hardware co-design. The hardware processing unit comprises engines such as convolution, grid sampling, upsample, etc. Parallelization optimization strategies like double-buffered pipelines and loop unrolling are employed to fully exploit the resources of FPGA. Ultimately, we establish an AGC FPGA prototype on the PYNQ-Z1 platform using the proposed scheme, achieving \textbf{24.9$\times$} and \textbf{4.1$\times$} higher energy efficiency against commercial Central Processing Unit (CPU) and Graphic Processing Unit (GPU), respectively. Specifically, only \textbf{11.7} microjoules ($\upmu$J) are required for one pixel reconstructed by this FPGA system.