Modeling Closed-loop Analog Matrix Computing Circuits with Interconnect Resistance

TL;DR

This paper models the effects of interconnect resistance on analog matrix computing circuits, introduces fast algorithms for key operations, and develops a bias-based compensation method to improve accuracy and scalability.

Contribution

It presents novel fast solving algorithms exploiting sparsity for AMC circuit operations and a bias-based error mitigation strategy, enhancing accuracy and scalability.

Findings

Algorithms achieve several orders of magnitude speedup over SPICE.

Bias-based compensation reduces errors by over 50% for INV and 70% for EGV.

The approach reveals how optimal bias scales with matrix size and interconnect resistance.

Abstract

Analog matrix computing (AMC) circuits based on resistive random-access memory (RRAM) have shown strong potential for accelerating matrix operations. However, as matrix size grows, interconnect resistance increasingly degrades computational accuracy and limits circuit scalability. Modeling and evaluating these effects are therefore critical for developing effective mitigation strategies. Traditional SPICE (Simulation Program with Integrated Circuit Emphasis) simulators, which rely on modified nodal analysis, become prohibitively slow for large-scale AMC circuits due to the quadratic growth of nodes and feedback connections. In this work, we model AMC circuits with interconnect resistance for two key operations-matrix inversion (INV) and eigenvector computation (EGV), and propose fast solving algorithms tailored for each case. The algorithms exploit the sparsity of the Jacobian matrix, enabling rapid and accurate solutions. Compared to SPICE, they achieve several orders of magnitude acceleration while maintaining high accuracy. We further extend the approach to open-loop matrix-vector multiplication (MVM) circuits, demonstrating similar efficiency gains. Finally, leveraging these fast solvers, we develop a bias-based compensation strategy that reduces interconnect-induced errors by over 50% for INV and 70% for EGV circuits. It also reveals the scaling behavior of the optimal bias with respect to matrix size and interconnect resistance.