An MLIR pipeline for offloading Fortran to FPGAs via OpenMP

TL;DR

This paper introduces a novel MLIR-based compilation pipeline that enables selective offloading of Fortran code to FPGAs using OpenMP directives, enhancing portability and flexibility for heterogeneous HPC acceleration.

Contribution

It presents the first implementation of OpenMP target offloading to FPGAs within MLIR, integrating with Flang and supporting manual kernel optimization.

Findings

Supports portable FPGA offloading via MLIR and OpenMP

Reduces development effort through MLIR ecosystem integration

Enables manual optimization of offloaded kernels

Abstract

With the slowing of Moore's Law, heterogeneous computing platforms such as Field Programmable Gate Arrays (FPGAs) have gained increasing interest for accelerating HPC workloads. In this work we present, to the best of our knowledge, the first implementation of selective code offloading to FPGAs via the OpenMP target directive within MLIR. Our approach combines the MLIR OpenMP dialect with a High-Level Synthesis (HLS) dialect to provide a portable compilation flow targeting FPGAs. Unlike prior OpenMP FPGA efforts that rely on custom compilers, by contrast we integrate with MLIR and so support any MLIR-compatible front end, demonstrated here with Flang. Building upon a range of existing MLIR building blocks significantly reduces the effort required and demonstrates the composability benefits of the MLIR ecosystem. Our approach supports manual optimisation of offloaded kernels through standard OpenMP directives, and this work establishes a flexible and extensible path for directive-based FPGA acceleration integrated within the MLIR ecosystem.