DRACO: Co-design for DSP-Efficient Rigid Body Dynamics Accelerator

TL;DR

This paper introduces a FPGA-based RBD accelerator with novel quantization, division deferring, and DSP reuse techniques, achieving significant throughput and latency improvements for robotic systems.

Contribution

It presents a comprehensive hardware co-design approach for efficient RBD acceleration, including quantization, division optimization, and DSP reuse, with extensive evaluation.

Findings

Up to 8x throughput improvement

7.4x latency reduction

Effective scalability for high-DOF robots

Abstract

We propose a hardware-efficient RBD accelerator based on FPGA, introducing three key innovations. First, we propose a precision-aware quantization framework that reduces DSP demand while preserving motion accuracy. This is also the first study to systematically evaluate quantization impact on robot control and motion for hardware acceleration. Second, we leverage a division deferring optimization in mass matrix inversion algorithm, which decouples reciprocal operations from the longest latency path to improve the performance. Finally, we present an inter-module DSP reuse methodology to improve DSP utilization and save DSP usage. Experiment results show that our work achieves up to 8x throughput improvement and 7.4x latency reduction over state-of-the-art RBD accelerators across various robot types, demonstrating its effectiveness and scalability for high-DOF robotic systems.