A Dual-Memory Ferroelectric Transistor Emulating Synaptic Metaplasticity for High-Speed Reservoir Computing

TL;DR

This paper presents a CMOS-compatible ferroelectric transistor with dual-memory capabilities, enabling high-speed, energy-efficient reservoir computing for edge AI by emulating synaptic metaplasticity.

Contribution

It introduces a novel ferroelectric transistor that combines non-volatile and volatile memory, facilitating scalable, reconfigurable reservoir computing with improved speed and energy efficiency.

Findings

Achieves 20 microsecond response time, 1000 times faster than previous systems.

Reduces reservoir states needed for tasks by approximately five times.

Demonstrates low energy consumption of 1.5 x 10^-7 Joules per operation.

Abstract

The exponential growth of edge artificial intelligence demands material-focused solutions to overcome energy consumption and latency limitations when processing real-time temporal data. Physical reservoir computing (PRC) offers an energy-efficient paradigm but faces challenges due to limited device scalability and reconfigurability. Additionally, reservoir and readout layers require memory of different timescales, short-term and long-term respectively - a material challenge hindering CMOS-compatible implementations. This work demonstrates a CMOS-compatible ferroelectric transistor using hafnium-zirconium-oxide (HZO) and silicon, enabling dual-memory operation. This system exhibits non-volatile long-term memory (LTM) from ferroelectric HZO polarization and volatile short-term memory (STM) from engineered non-quasi-static (NQS) channel-charge relaxation driven by gate-source/drain overlap capacitance. Ferroelectric polarization acts as non-volatile programming of volatile dynamics: by modulating threshold voltage, the ferroelectric state deterministically switches the NQS time constant and computational behavior between paired-pulse facilitation (PPF) and depression (PPD). This establishes a generalizable material-design principle applicable to diverse ferroelectric-semiconductor heterostructures, extending beyond silicon to oxide semiconductors and heterogeneously-integrated systems. The device solves second-order nonlinear tasks with 3.69 x 10^-3 normalized error using only 16 reservoir states - ~5x reduction - achieving 20 us response time (~1000x faster) and 1.5 x 10^-7 J energy consumption, providing an immediately manufacturable pathway for neuromorphic hardware and energy-efficient edge intelligence.