ASTER: Attention-based Spiking Transformer Engine for Event-driven Reasoning
Tamoghno Das, Khanh Phan Vu, Hanning Chen, Hyunwoo Oh, Mohsen Imani

TL;DR
This paper introduces a specialized hardware accelerator for spiking transformer models, combining analog-digital PIM architecture and software optimizations to enable efficient, low-power, real-time event-driven visual reasoning on edge devices.
Contribution
The work presents a novel memory-centric hybrid analog-digital PIM accelerator and inference optimizations tailored for spiking transformers, addressing hardware and algorithmic challenges.
Findings
Achieves up to 467x energy reduction over edge GPU
Maintains competitive accuracy on ImageNet
Enables low-power real-time event-driven visual processing
Abstract
The integration of spiking neural networks (SNNs) with transformer-based architectures has opened new opportunities for bio-inspired low-power, event-driven visual reasoning on edge devices. However, the high temporal resolution and binary nature of spike-driven computation introduce architectural mismatches with conventional digital hardware (CPU/GPU). Prior neuromorphic and Processing-in-Memory (PIM) accelerators struggle with high sparsity and complex operations prevalent in such models. To address these challenges, we propose a memory-centric hardware accelerator tailored for spiking transformers, optimized for deployment in real-time event-driven frameworks such as classification with both static and event-based input frames. Our design leverages a hybrid analog-digital PIM architecture with input sparsity optimizations, and a custom-designed dataflow to minimize memory access…
Peer Reviews
No public reviews on file for this paper yet. If you reviewed it on a platform where reviews are public (OpenReview, ICLR, NeurIPS, ICML), you can paste yours below so the community can read it here.
Videos
No videos yet. Explain this paper in a talk, walkthrough, or lecture? Add one.
Taxonomy
TopicsAdvanced Memory and Neural Computing · Ferroelectric and Negative Capacitance Devices · Neural Networks and Reservoir Computing
