Reconfigurable Quantum Instruction Set Computers for High Performance Attainable on Hardware
Zhaohui Yang, Dawei Ding, Qi Ye, Cupjin Huang, Jianxin Chen, Yuan Xie

TL;DR
This paper introduces ReQISC, a reconfigurable quantum instruction set architecture that enables more efficient quantum gate implementation, significantly reducing pulse durations and improving overall quantum circuit performance on hardware.
Contribution
The paper presents a novel reconfigurable quantum ISA with a unified microarchitecture and tailored compiler framework, making continuous ISAs practically feasible for quantum hardware.
Findings
4.97-fold reduction in average pulse duration for 2Q gates
Significant decrease in circuit depth and gate counts
Improved program fidelity and hardware mapping efficiency
Abstract
The performance of current quantum hardware is severely limited. While expanding the quantum ISA with high-fidelity, expressive basis gates is a key path forward, it imposes significant gate calibration overhead and complicates compiler optimization. As a result, even though more powerful ISAs have been designed, their use remains largely conceptual rather than practical. To move beyond these hurdles, we introduce the concept of "reconfigurable quantum instruction set computers" (ReQISC), which incorporates: (1) a unified microarchitecture capable of directly implementing arbitrary 2Q gates equivalently, i.e., SU(4) modulo 1Q rotations, with theoretically optimal gate durations given any 2Q coupling Hamiltonians; (2) a compilation framework tailored to ReQISC primitives for end-to-end synthesis and optimization, comprising a program-aware pass that refines high-level representations,…
Peer Reviews
No public reviews on file for this paper yet. If you reviewed it on a platform where reviews are public (OpenReview, ICLR, NeurIPS, ICML), you can paste yours below so the community can read it here.
Videos
No videos yet. Explain this paper in a talk, walkthrough, or lecture? Add one.
