Guidelines for Building Indexes on Partially Cache-Coherent CXL Shared Memory
Fangnuo Wu, Mingkai Dong, Wenjun Cai, Jingsheng Yan, Haibo Chen

TL;DR
This paper proposes guidelines for building consistent and efficient indexes on Partially Cache-Coherent (PCC) platforms using CXL technology, addressing correctness and performance challenges through synchronization and optimization techniques.
Contribution
It introduces SP and P^3 guidelines for converting and optimizing indexes on PCC platforms, significantly improving their throughput and performance.
Findings
Converted indexes' throughput improves up to 16× with P^3 guidelines.
Optimized indexes outperform message-passing and disaggregated-memory counterparts by up to 16× and 19×.
Proposed methods effectively address correctness and efficiency issues on PCC platforms.
Abstract
The \emph{Partial Cache-Coherence (PCC)} model maintains hardware cache coherence only within subsets of cores, enabling large-scale memory sharing with emerging memory interconnect technologies like Compute Express Link (CXL). However, PCC's relaxation of global cache coherence compromises the correctness of existing single-machine software. This paper focuses on building consistent and efficient indexes on PCC platforms. We present that existing indexes designed for cache-coherent platforms can be made consistent on PCC platforms following SP guidelines, i.e., we identify \emph{sync-data} and \emph{protected-data} according to the index's concurrency control mechanisms, and synchronize them accordingly. However, conversion with SP guidelines introduces performance overhead. To mitigate the overhead, we identify several unique performance bottlenecks on PCC platforms, and propose…
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Taxonomy
TopicsParallel Computing and Optimization Techniques · Cloud Computing and Resource Management · Distributed systems and fault tolerance
