Automating Hardware Design and Verification from Architectural Papers via a Neural-Symbolic Graph Framework

TL;DR

This paper introduces ArchCraft, a neural-symbolic framework that automates converting academic architectural descriptions into synthesizable hardware designs, enabling verification and benchmarking with superior accuracy and efficiency.

Contribution

We propose ArchCraft, the first framework to translate academic architectural papers into verified RTL hardware designs and introduce ArchSynthBench, a comprehensive benchmark for evaluation.

Findings

ArchCraft outperforms existing methods in understanding and code generation.

Generated RTL designs meet timing constraints and match original performance metrics.

ArchSynthBench provides a standardized evaluation platform with 50 circuits and 600 blocks.

Abstract

The reproduction of hardware architectures from academic papers remains a significant challenge due to the lack of publicly available source code and the complexity of hardware description languages (HDLs). To this end, we propose \textbf{ArchCraft}, a Framework that converts abstract architectural descriptions from academic papers into synthesizable Verilog projects with register-transfer level (RTL) verification. ArchCraft introduces a structured workflow, which uses formal graphs to capture the Architectural Blueprint and symbols to define the Functional Specification, translating unstructured academic papers into verifiable, hardware-aware designs. The framework then generates RTL and testbench (TB) code decoupled via these symbols to facilitate verification and debugging, ultimately reporting the circuit's Power, Area, and Performance (PPA). Moreover, we propose the first benchmark, \textbf{ArchSynthBench}, for synthesizing hardware from architectural descriptions, with a complete set of evaluation indicators, 50 project-level circuits, and around 600 circuit blocks. We systematically assess ArchCraft on ArchSynthBench, where the experiment results demonstrate the superiority of our proposed method, surpassing direct generation methods and the VerilogCoder framework in both paper understanding and code completion. Furthermore, evaluation and physical implementation of the generated executable RTL code show that these implementations meet all timing constraints without violations, and their performance metrics are consistent with those reported in the original papers.