Delay Time Characterization on FPGA: A Low Nonlinearity, Picosecond Resolution Time-to-Digital Converter on 16-nm FPGA using Bin Sequence Calibration

TL;DR

This paper introduces a high-resolution, low-nonlinearity FPGA-based TDC with 1.15 ps resolution, utilizing novel hardware-independent calibration techniques to enhance performance and scalability in precise time measurement.

Contribution

It presents two innovative, hardware-independent post-processing methods, POR and ITI, that significantly improve FPGA TDC accuracy and resolution without additional hardware complexity.

Findings

Achieved 1.15 ps resolution on 16 nm FPGA

Introduced POR and ITI calibration techniques

Demonstrated superior performance over existing TDCs

Abstract

We present a Time-to-Digital Converter (TDC) implemented on a 16 nm Xilinx UltraScale Plus FPGA that achieves a resolution of 1.15 ps, RMS precision of 3.38 ps, a differential nonlinearity (DNL) of [-0.43, 0.24] LSB, and an integral nonlinearity (INL) of [-2.67, 0.15] LSB. This work introduces two novel hardware-independent post-processing techniques - Partial Order Reconstruction (POR) and Iterative Time-bin Interleaving (ITI) - that significantly enhance the performance of FPGA-based TDCs. POR addresses the missing code problem by inferring the partial order of each time bin through code density test data and directed acyclic graph (DAG) analysis, enabling near-complete recovery of usable bins. ITI further improves fine time resolution by merging multiple calibrated tapped delay lines (TDLs) into a single unified delay chain, achieving scalable resolution without resorting to averaging. Compared to state-of-the-art FPGA-based TDC architectures, the proposed methods deliver competitive or superior performance with reduced hardware overhead. These techniques are broadly applicable to high-resolution time measurement and precise delay calibration in programmable logic platforms.