Realization of Thread Level Parallelism on Quantum Devices

TL;DR

This paper presents a classical linkage scheme that enables thread-level parallelism in quantum devices, demonstrated on NMR quantum nodes, allowing scalable quantum computation with existing hardware.

Contribution

The authors introduce a novel classical linkage architecture that merges multiple quantum processing units to achieve parallelism and scalability in quantum computing.

Findings

Validated on up to sixteen NMR quantum nodes

Achieved 93.8% fidelity in GHZ state partitioning

Reproduced non-Hermitian evolution with high accuracy

Abstract

Scaling up quantum devices is a central challenge for realizing practical quantum computation. Modular quantum architectures promise scalability, yet experiments to date have relied on either $\sim\!10^{3}$-qubit monolithic chips or fragile interconnects with high loss. Here, we introduce a classical linkage scheme that merges multiple independent quantum processing units (QPUs) into a single logical device, enabling thread-level parallelism (TLP). Theoretically, we show that quantum routines with product-state inputs and low-rank entangling layers can be re-expressed in an efficient parallelizable form. Experimentally, we validate this architecture on clusters comprising up to sixteen benchtop nuclear magnetic resonance (NMR) quantum nodes. A four-qubit Greenberger-Horne-Zeilinger (GHZ) state is partitioned into parallel two-qubit subcircuits, achieving a fidelity of $93.8\,\%$ with respect to the ideal state. A non-Hermitian evolution, implemented via a truncated Cauchy integral on Hermitian Hamiltonians, reproduces exact observables with high accuracy. Our results demonstrate that classical links suffice to scale up the logical size of quantum computations and realize general, non-unitary channels on today's hardware, opening an experimentally accessible route toward software-defined, clustered quantum accelerators.