Mapping the positions of Two-Level-Systems on the surface of a superconducting transmon qubit

TL;DR

This paper introduces a method to locate individual two-level-systems (TLS) on a superconducting transmon qubit surface, aiding in understanding and mitigating decoherence caused by material defects.

Contribution

A novel on-chip electric field tuning technique is developed to map the positions of TLS on a transmon qubit surface, revealing their distribution and impact on qubit coherence.

Findings

Most TLS are located on qubit leads, not the capacitor.

TLS density is higher near shadow-evaporated electrodes.

The method helps identify circuit regions critical for decoherence.

Abstract

The coherence of superconducting quantum computers is severely limited by material defects that create parasitic two-level-systems (TLS). Progress is complicated by lacking understanding how TLS are created and in which parts of a qubit circuit they are most detrimental. Here, we present a method to determine the individual positions of TLS at the surface of a transmon qubit. We employ a set of on-chip gate electrodes near the qubit to generate local DC electric fields that are used to tune the TLS' resonance frequencies. The TLS position is inferred from the strengths at which TLS couple to different electrodes and comparing them to electric field simulations. We found that the majority of detectable surface-TLS was residing on the leads of the qubit's Josephson junction, despite the dominant contribution of its coplanar capacitor to electric field energy and surface area. This indicates that the TLS density is significantly enhanced near shadow-evaporated electrodes fabricated by lift-off techniques. Our method is useful to identify critical circuit regions where TLS contribute most to decoherence, and can guide improvements in qubit design and fabrication methods.