MultiVic: A Time-Predictable RISC-V Multi-Core Processor Optimized for Neural Network Inference

TL;DR

MultiVic introduces a predictable, multi-core RISC-V architecture optimized for neural network inference, balancing high performance with strict timing guarantees essential for real-time applications.

Contribution

It presents a novel multi-core vector processor design with predictable cores and a static memory access schedule, enhancing both performance and timing predictability.

Findings

More cores with smaller size improve performance and memory bandwidth.

Execution time fluctuation remains very low, ensuring predictability.

Configurations with increased cores outperform single-core baselines.

Abstract

Real-time systems, particularly those used in domains like automated driving, are increasingly adopting neural networks. From this trend arises the need for high-performance hardware exhibiting predictable timing behavior. While state-of-the-art real-time hardware often suffers from limited memory and compute resources, modern AI accelerators typically lack the crucial predictability due to memory interference. We present a new hardware architecture to bridge this gap between performance and predictability. The architecture features a multi-core vector processor with predictable cores, each equipped with local scratchpad memories. A central management core orchestrates access to shared external memory following a statically determined schedule. To evaluate the proposed hardware architecture, we analyze different variants of our parameterized design. We compare these variants to a baseline architecture consisting of a single-core vector processor with large vector registers. We find that configurations with a larger number of smaller cores achieve better performance due to increased effective memory bandwidth and higher clock frequencies. Crucially for real-time systems, execution time fluctuation remains very low, demonstrating the platform's time predictability.