Hardware-Accelerated GNN-based Hit Filtering for the Belle II Level-1 Trigger

TL;DR

This paper introduces a hardware-accelerated GNN-based hit filtering system on FPGAs for the Belle II experiment, achieving real-time processing with high background suppression and low latency.

Contribution

It presents a novel FPGA implementation of GNN-based hit filtering with optimizations for high throughput and scalability in collider trigger systems.

Findings

Processes data at 31.804 MHz in real-time

Achieves 83% background hit rejection

Latency of 632.4 ns with low resource usage

Abstract

We present a hardware-accelerated hit filtering system employing Graph Neural Networks (GNNs) on Field-Programmable Gate Arrays (FPGAs) for the Belle II Level-1 Trigger. The GNN exploits spatial and temporal relationships among sense wire hits and is optimized for high-throughput hardware operation via quantization, pruning, and static graph-building. Sector-wise spatial parallelization permits scaling to full-detector coverage, satisfying stringent latency and throughput requirements. At a sustained throughput of 31.804 MHz, the system processes sense wire data in real-time and achieves detector-level background suppression with a measured latency of 632.4 ns while utilizing 35.65% of Look-Up Tables (LUTs), and 29.75% of Flip-Flops, with zero Digital Signal Processing (DSP) usage, as demonstrated in a prototype implementation for a single sector on an AMD Ultrascale XVCU190. Offline validation using Belle II data yields a background hit rejection of 83% while maintaining 95% signal hit efficiency. This work establishes hit-level GNN-based filtering on FPGAs as a scalable low-latency solution for real-time data reduction in high-luminosity collider conditions.