Implementation of transformer-based LLMs with large-scale optoelectronic neurons on a CMOS compatible platform
Neil Na, Chih-Hao Cheng, Shou-Chen Hsu, Che-Fu Liang, Chung-Chih Lin, Nathaniel Y. Na, Andrew I. Shieh, Erik Chen, Haisheng Rong, Richard A. Soref

TL;DR
This paper presents a CMOS-compatible optoelectronic neuron platform enabling ultra-fast, energy-efficient large-scale transformer-based LLM inference with minimal hardware errors, offering a practical path for analog neural processing units.
Contribution
It introduces a novel large-scale optoelectronic neuron implementation on CMOS platform for transformer models, achieving high speed and efficiency in LLM inference.
Findings
Inference speed of 12.6 POPS for GPT-3 with 175 billion parameters.
Power efficiency of 74 TOPS/W and area efficiency of 19 TOPS/mm2.
Minimal impact of quantization and hardware errors on performance.
Abstract
The recent rapid deployment of datacenter infrastructures for performing large language models (LLMs) and related artificial intelligence (AI) applications in the clouds is predicted to incur an exponentially growing energy consumption in the near-term future. In this paper, we propose and analyze the implementation of the transformer model, which is the cornerstone of the modern LLMs, with novel large-scale optoelectronic neurons (OENs) constructed over a complementary metal-oxide-semiconductor (CMOS) compatible platform. With all of the required optoelectronic devices and electronic circuits integrated in a chiplet only about 2 cm by 3 cm in size, 175 billon parameters in the case of GPT-3 are shown to perform inference at an unprecedented speed of 12.6 POPS using only 40 nm CMOS process node, orchestrated by an optoelectronic version of systolic array with no data skew and negligible…
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