LogHD: Robust Compression of Hyperdimensional Classifiers via Logarithmic Class-Axis Reduction

TL;DR

LogHD introduces a logarithmic class-axis reduction method for hyperdimensional classifiers, significantly reducing memory while maintaining robustness and accuracy, and achieving substantial energy and speed improvements.

Contribution

It proposes a novel logarithmic class-axis reduction technique that enhances robustness and efficiency of hyperdimensional classifiers compared to prior methods.

Findings

Achieves competitive accuracy with smaller models.

Provides higher resilience to bit flips at matched memory.

Delivers substantial energy efficiency and speedup in ASIC implementations.

Abstract

Hyperdimensional computing (HDC) suits memory, energy, and reliability-constrained systems, yet the standard "one prototype per class" design requires $O(CD)$ memory (with $C$ classes and dimensionality $D$). Prior compaction reduces $D$ (feature axis), improving storage/compute but weakening robustness. We introduce LogHD, a logarithmic class-axis reduction that replaces the $C$ per-class prototypes with $n\!\approx\!\lceil\log_k C\rceil$ bundle hypervectors (alphabet size $k$) and decodes in an $n$-dimensional activation space, cutting memory to $O(D\log_k C)$ while preserving $D$. LogHD uses a capacity-aware codebook and profile-based decoding, and composes with feature-axis sparsification. Across datasets and injected bit flips, LogHD attains competitive accuracy with smaller models and higher resilience at matched memory. Under equal memory, it sustains target accuracy at roughly $2.5$-$3.0\times$ higher bit-flip rates than feature-axis compression; an ASIC instantiation delivers $498\times$ energy efficiency and $62.6\times$ speedup over an AMD Ryzen 9 9950X and $24.3\times$/$6.58\times$ over an NVIDIA RTX 4090, and is $4.06\times$ more energy-efficient and $2.19\times$ faster than a feature-axis HDC ASIC baseline.