Challenges and strategies in verification of FastRICH ASIC for the LHCb RICH detector

TL;DR

This paper discusses the verification strategies for the FastRICH ASIC, a high-precision, triggerless readout chip for the LHCb RICH detector, addressing challenges in ensuring performance across various operational conditions.

Contribution

It introduces a comprehensive verification methodology for FastRICH, including simulations and stress testing, to ensure functional correctness and timing performance under high-rate conditions.

Findings

FastRICH meets performance requirements across occupancy scenarios

Verification strategy effectively ensures timing precision and robustness

Lessons learned inform future ASIC development for high-rate detectors

Abstract

The FastRICH ASIC provides high-precision, triggerless readout for the LS3 Enhancements and Upgrades II of the LHCb RICH detector. The demands of continuous data acquisition and varying hit rates across the detector impose unique challenges on the ASIC's design and verification. This work presents the verification strategy for FastRICH, focusing on functional correctness, timing performance, and operational robustness. The methodology includes simulations across occupancy scenarios, validation of timing precision, and stress testing under pile-up and high-rate conditions. Results demonstrate that FastRICH meets its performance requirements over the full range of expected occupancies. Key design and verification challenges specific to triggerless, fast-timing ASICs are discussed, along with lessons learned for future developments.