LogicSparse: Enabling Engine-Free Unstructured Sparsity for Quantised Deep-learning Accelerators

TL;DR

This paper presents LogicSparse, a framework that integrates unstructured sparsity into FPGA-based QNN accelerators, improving efficiency and throughput without specialized hardware, demonstrated on LeNet-5.

Contribution

It introduces a hardware-aware pruning method and a dataflow architecture that exploits unstructured sparsity without dedicated sparse engines.

Findings

Achieves 51.6x compression on LeNet-5.

Attains 1.23x throughput improvement.

Uses only 5.12% of LUTs for acceleration.

Abstract

FPGAs have been shown to be a promising platform for deploying Quantised Neural Networks (QNNs) with high-speed, low-latency, and energy-efficient inference. However, the complexity of modern deep-learning models limits the performance on resource-constrained edge devices. While quantisation and pruning alleviate these challenges, unstructured sparsity remains underexploited due to irregular memory access. This work introduces a framework that embeds unstructured sparsity into dataflow accelerators, eliminating the need for dedicated sparse engines and preserving parallelism. A hardware-aware pruning strategy is introduced to improve efficiency and design flow further. On LeNet-5, the framework attains 51.6 x compression and 1.23 x throughput improvement using only 5.12% of LUTs, effectively exploiting unstructured sparsity for QNN acceleration.