Digit-Recurrence Posit Division

TL;DR

This paper introduces a novel radix-4 digit-recurrence division algorithm for posit arithmetic units, achieving significant energy savings and performance improvements through hardware optimizations.

Contribution

First implementation of radix-4 digit-recurrence division in posit systems with hardware optimizations for efficiency.

Findings

Over 80% energy reduction compared to existing methods

Significant decrease in division iteration count

Small area overhead with improved performance

Abstract

Posit arithmetic has emerged as a promising alternative to IEEE 754 floating-point representation, offering enhanced accuracy and dynamic range. However, division operations in posit systems remain challenging due to their inherent hardware complexity. In this work, we present posit division units based on the digit-recurrence algorithm, marking the first implementation of radix-4 digit-recurrence techniques within this context. Our approach incorporates hardware-centric optimizations including redundant arithmetic, on-the-fly quotient conversion, and operand scaling to streamline the division process while mitigating latency, area, and power overheads. Comprehensive synthesis evaluations across multiple posit configurations demonstrate significant performance improvements, including more than 80% energy reduction with small area overhead compared to existing methods, and a substantial decrease in the number of iterations. These results underscore the potential of our adapted algorithm to enhance the efficiency of posit-based arithmetic units.