VFocus: Better Verilog Generation from Large Language Model via Focused Reasoning

TL;DR

VFocus is a three-stage framework that improves Verilog code generation from large language models by focusing reasoning on critical parts, filtering, testing, and refining candidates to enhance correctness.

Contribution

VFocus introduces a novel multi-stage approach with density-guided filtering, simulation-based ranking, and reasoning-augmented refinement to significantly improve LLM-generated Verilog code quality.

Findings

Significantly improves pass@1 correctness on VerilogEval-Human benchmark.

Effective in complex hardware design tasks with multiple reasoning LLMs.

Demonstrates the benefit of focused reasoning and candidate refinement in code generation.

Abstract

Large Language Models (LLMs) have shown impressive potential in generating Verilog codes, but ensuring functional correctness remains a challenge. Existing approaches often rely on self-consistency or simulation feedback to select the best candidate, but they miss opportunities to focus LLM reasoning on the most informative parts of the design. We propose VFocus, a three-stage framework that enhances Verilog generation by sharpening the focus of LLM reasoning onto critical decision points in the code generation process. In the \textbf{pre-ranking stage}, VFocus generates multiple code candidates through LLM prompting, retries for syntactically valid outputs, and introduces a \textit{Density-guided Filtering} to retain candidates that fall within the "reasoning sweet spot" for functional correctness. In the \textbf{ranking stage}, we simulate each code candidate using an automatically generated testbench and apply self-consistency-based clustering to identify the most consistent outputs. Finally, in the \textbf{post-ranking refinement stage}, VFocus performs inconsistency mining on top-ranked candidates and invokes reasoning-augmented LLM prompts for candidate refinement. Experiments on the VerilogEval-Human benchmark show that VFocus significantly improves the pass@1 correctness across multiple reasoning LLMs, demonstrating its effectiveness in enhancing Verilog generation for complex hardware design tasks.