Multiplexed double-transmon coupler scheme in scalable superconducting quantum processor

TL;DR

This paper introduces a double-transmon coupler architecture that reduces wiring complexity and maintains high-fidelity gate operations, advancing the scalability of superconducting quantum processors.

Contribution

It proposes a multiplexed control scheme using a double-transmon coupler, demonstrating reduced wiring and effective suppression of static ZZ coupling while preserving gate fidelity.

Findings

Achieved Bell state fidelity >99%.

Prepared three-qubit GHZ states with >96% fidelity.

Validated suppression of static ZZ coupling.

Abstract

Precise control of superconducting qubits is essential for advancing both quantum simulation and quantum error correction. Recently, transmon qubit systems employing the single-transmon coupler (STC) scheme have demonstrated high-fidelity single- and two-qubit gate operations by dynamically tuning the effective coupling between qubits. However, the integration of STCs increases the number of control lines, thereby posing a significant bottleneck for chip routing and scalability. To address this challenge, we propose a robust control line multiplexing scheme based on a double-transmon coupler (DTC) architecture, which enables shared coupler control lines to substantially reduce wiring complexity. Moreover, we experimentally verify that this multiplexed configuration efficiently suppresses undesirable static $ZZ$ coupling while maintaining accurate control over two-qubit gate operations. We further demonstrate the feasibility of the architecture through two distinct gate implementations: a fast coupler $Z$-control-based CZ gate and a parametric iSWAP gate. To validate the practical applicability of this multiplexing approach in quantum circuits, we prepare Bell and three-qubit GHZ states using the proposed scheme with fidelity exceeding 99% and 96%, respectively. This multiplexed DTC architecture offers significant potential to minimize wiring overhead in two-dimensional qubit arrays, thereby greatly enhancing the scalability of superconducting quantum processors.