Simulation-Driven Evaluation of Chiplet-Based Architectures Using VisualSim

TL;DR

This paper presents a detailed simulation framework using VisualSim to evaluate chiplet-based multi-die SoC architectures, focusing on performance, communication, and power tradeoffs.

Contribution

It introduces a comprehensive simulation model for chiplet-based systems, enabling performance analysis and optimization of multi-chip configurations.

Findings

Identifies key factors affecting chiplet system performance.

Provides insights into inter-chiplet communication latency.

Highlights power-performance tradeoffs under various workloads.

Abstract

This paper focuses on the simulation of multi-die System-on-Chip (SoC) architectures using VisualSim, emphasizing chiplet-based system modeling and performance analysis. Chiplet technology presents a promising alternative to traditional monolithic chips, which face increasing challenges in manufacturing costs, power efficiency, and performance scaling. By integrating multiple small modular silicon units into a single package, chiplet-based architectures offer greater flexibility and scalability at a lower overall cost. In this study, we developed a detailed simulation model of a chiplet-based system, incorporating multicore ARM processor clusters interconnected through a ARM CMN600 network-on-chip (NoC) for efficient communication [4], [7]. The simulation framework in VisualSim enables the evaluation of critical system metrics, including inter-chiplet communication latency, memory access efficiency, workload distribution, and the power-performance tradeoff under various workloads. Through simulation-driven insights, this research highlights key factors influencing chiplet system performance and provides a foundation for optimizing future chiplet-based semiconductor designs.