A High-Throughput Spiking Neural Network Processor Enabling Synaptic Delay Emulation

TL;DR

This paper presents a high-throughput SNN processor supporting synaptic delay emulation, enabling real-time edge applications with high accuracy and efficiency on FPGA hardware.

Contribution

It introduces a multicore pipelined architecture for SNNs that efficiently emulates synaptic delays, demonstrated on an FPGA platform for low-power, real-time processing.

Findings

Achieves 93.4% accuracy on SHD benchmark

Processes 104 samples/sec at 125 MHz

Consumes 282 mW power

Abstract

Synaptic delay has attracted significant attention in neural network dynamics for integrating and processing complex spatiotemporal information. This paper introduces a high-throughput Spiking Neural Network (SNN) processor that supports synaptic delay-based emulation for edge applications. The processor leverages a multicore pipelined architecture with parallel compute engines, capable of real-time processing of the computational load associated with synaptic delays. We develop a SoC prototype of the proposed processor on PYNQ Z2 FPGA platform and evaluate its performance using the Spiking Heidelberg Digits (SHD) benchmark for low-power keyword spotting tasks. The processor achieves 93.4% accuracy in deployment and an average throughput of 104 samples/sec at a typical operating frequency of 125 MHz and 282 mW power consumption.