Gate Dielectric Engineering with an Ultrathin Silicon-oxide Interfacial Dipole Layer for Low-Leakage Oxide-Semiconductor Memories

TL;DR

This paper introduces an ultrathin silicon oxide interfacial layer in oxide-semiconductor memories that enhances threshold voltage control, improves reliability, and significantly reduces leakage current, enabling more stable and energy-efficient memory devices.

Contribution

The study presents a novel gate dielectric engineering method using an ALD silicon oxide layer that achieves multi-level V$_T$ control and reduces leakage without high-temperature processing.

Findings

Achieves at least four distinct V$_T$ levels with up to 500 mV shift.

Reduces negative V$_T$ shifts under bias temperature stress, indicating improved reliability.

Decreases standby leakage current by three orders of magnitude, enhancing energy efficiency.

Abstract

We demonstrate a gate dielectric engineering approach leveraging an ultrathin, atomic layer deposited (ALD) silicon oxide interfacial layer (SiL) between the amorphous oxide semiconductor (AOS) channel and the high-k gate dielectric. SiL positively shifts the threshold voltage (V$_T$) of AOS transistors, providing at least four distinct $V_T$ levels with a maximum increase of 500 mV. It achieves stable $V_T$ control without significantly degrading critical device parameters such as mobility, on-state current, all while keeping the process temperature below 225 $^{\circ}$C and requiring no additional heat treatment to activate the dipole. Positive-bias temperature instability tests at 85 $^{\circ}$C indicate a significant reduction in negative $V_{T}$ shifts for SiL-integrated devices, highlighting enhanced reliability. Incorporating this SiL gate stack into two-transistor gain-cell (GC) memory maintains a more stable storage node voltage ($V_{SN}$) (reduces $V_{SN}$ drop by 67\%), by limiting unwanted charge losses. SiL-engineered GCs also reach retention times up to 10,000 s at room temperature and reduce standby leakage current by three orders of magnitude relative to baseline device, substantially lowering refresh energy consumption.