FeNN-DMA: A RISC-V SoC for SNN acceleration

TL;DR

FeNN-DMA is a novel RISC-V-based FPGA system-on-chip designed for efficient simulation of spiking neural networks, supporting complex models and achieving state-of-the-art accuracy on multiple neuromorphic tasks.

Contribution

The paper introduces FeNN-DMA, a fully-programmable RISC-V SoC for SNN acceleration on FPGAs, enabling complex models and large-scale simulations with competitive energy use.

Findings

Supports up to 16,000 neurons and 256 million synapses per core.

Achieves state-of-the-art accuracy on neuromorphic classification tasks.

Comparable resource and energy efficiency to fixed-function accelerators.

Abstract

Spiking Neural Networks (SNNs) are a promising, energy-efficient alternative to standard Artificial Neural Networks (ANNs) and are particularly well-suited to spatio-temporal tasks such as keyword spotting and video classification. However, SNNs have a much lower arithmetic intensity than ANNs and are therefore not well-matched to standard accelerators like GPUs and TPUs. Field Programmable Gate Arrays (FPGAs) are designed for such memory-bound workloads, and here we present a novel, fully-programmable RISC-V-based system-on-chip (FeNN-DMA), tailored to simulating SNNs on modern UltraScale+ FPGAs. We show that FeNN-DMA has comparable resource usage and energy requirements to state-of-the-art fixed-function SNN accelerators, yet it supports more complex neuron models and network topologies, and can simulate up to 16 thousand neurons and 256 million synapses per core. Using this functionality, we demonstrate state-of-the-art classification accuracy on the Spiking Heidelberg Digits, Neuromorphic MNIST and Braille tactile classification tasks.