Descriptor-Based Object-Aware Memory Systems: A Comprehensive Review

TL;DR

This paper reviews descriptor-based object-aware memory systems, highlighting their role in enhancing security and efficiency by propagating high-level object semantics across hardware and software interfaces.

Contribution

It provides a comprehensive survey, introduces a taxonomy of addressing modes, and re-examines the CentroID model to advance understanding of object-aware memory architectures.

Findings

Addresses memory protection and management challenges

Introduces a taxonomy of descriptor addressing modes

Re-examines the CentroID model as a case study

Abstract

The security and efficiency of modern computing systems are fundamentally undermined by the absence of a native architectural mechanism to propagate high-level program semantics, such as object identity, bounds, and lifetime, across the hardware/software interface. This paper presents a comprehensive survey of the architectural paradigm designed to bridge this semantic gap: descriptor-based, object-aware memory systems. By elevating the descriptor to a first-class architectural abstraction, this paradigm enables hardware to dynamically acquire and enforce the rich semantics of software-defined objects. This survey systematically charts the evolution and current landscape of this approach. We establish the foundational concepts of memory objects and descriptors and introduce a novel taxonomy of descriptor addressing modes, providing a structured framework for analyzing and comparing diverse implementations. Our unified analysis reveals how this paradigm holistically addresses the intertwined challenges of memory protection, management, and processing. As a culminating case study, we re-examine the CentroID model, demonstrating how its hybrid tagged-pointer encoding and descriptor processing mechanisms embody the path toward practical and efficient object-aware designs. Finally, we outline how the explicit cross-layer communication of object semantics provides a foundational research direction for next-generation cache hierarchies, unified virtual memory, and even 128-bit architectures.