Characterization of the H2M Monolithic CMOS Sensor

TL;DR

This paper characterizes the H2M monolithic CMOS sensor, demonstrating high detection efficiency, low fake-hit rate, and effective backside thinning, with insights into in-pixel response non-uniformities and mitigation strategies.

Contribution

It introduces a novel monolithic pixel sensor in 65nm CMOS with integrated analog and digital processing, and provides comprehensive performance analysis and mitigation approaches.

Findings

MIP detection efficiency above 99% at ~205 electrons threshold

Backside thinning down to 21 micrometers does not degrade performance

Identification and simulation of in-pixel response non-uniformities

Abstract

The H2M (Hybrid-to-Monolithic) is a monolithic pixel sensor manufactured in a modified \SI{65}{\nano\meter}~CMOS imaging process with a small collection electrode. Its design addresses the challenges of porting an existing hybrid pixel detector architecture into a monolithic chip, using a digital-on-top design methodology, and developing a compact digital cell library. Each square pixel integrates an analog front-end and digital pulse processing with an 8-bit counter within a \SI{35}{\micro\meter}~pitch. This contribution presents the performance of H2M based on laboratory and test beam measurements, including a comparison with analog front-end simulations in terms of gain and noise. A particular emphasis is placed on backside thinning in order to reduce material budget, down to a total chip thickness of \SI{21}{\micro\meter} for which no degradation in MIP detection performance is observed. For all investigated samples, a MIP detection efficiency above \SI{99}{\%} is achieved below a threshold of approximately 205 electrons. At this threshold, the fake-hit rate corresponds to a matrix occupancy of fewer than one pixel per the \SI{500}{\nano\second}~frame. Measurements reveal a non-uniform in-pixel response, attributed to the formation of local potential wells in regions with low electric field. A simulation flow combining technology computer-aided design, Monte Carlo, and circuit simulations is used to investigate and describe this behavior, and is applied to develop mitigation strategies for future chip submissions with similar features.